Method and apparatus for layering cache and architectural specif

Details Method and apparatus for layering cache and architectural specif Method and apparatus for layering cache and architectural specif

1997-04-14

2000-02-29

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711 3, 711130, 711140, 711169, G06F 1200, G06F 1300

Patent

active

060322268

ABSTRACT:
Cache and architectural specific functions within a cache controller are layered and provided with generic interfaces, isolating the complexities of each and allowing the overall functionality to be further divided into distinct, largely autonomous functional units. Each functional unit handles a certain type of operation and may be easily replicated or removed from the design to provide a number of cache designs with varied price and performance.

REFERENCES:
patent: 4926363 (1990-05-01), Nix
patent: 5301278 (1994-04-01), Bowater et al.
patent: 5408229 (1995-04-01), Yabusaki et al.
patent: 5434993 (1995-07-01), Liencres et al.
patent: 5485590 (1996-01-01), Hyatt et al.
patent: 5535360 (1996-07-01), Cassetti
patent: 5537572 (1996-07-01), Michelsen et al.
patent: 5644753 (1997-07-01), Ebrahim et al.
patent: 5659715 (1997-08-01), Wu et al.
patent: 5671355 (1997-09-01), Collins
patent: 5752047 (1998-05-01), Darty et al.

Affiliated with

Also associated with

Rating

Method and apparatus for layering cache and architectural specif does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for layering cache and architectural specif, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for layering cache and architectural specif will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-692888