Synchronous semiconductor memory device and synchronous memory m

Static information storage and retrieval – Addressing – Sync/clocking

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36523001, 36523008, 36518905, G11C 800

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active

058154620

ABSTRACT:
A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.

REFERENCES:
patent: 5412615 (1995-05-01), Noro et al.
patent: 5631866 (1997-05-01), Oka et al.
patent: 5666323 (1997-09-01), Zagar
Nitta, Yasuhiko, et al: "A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture", IEEE, 1996.
Saeki, Takanon, et al: "A 2.5ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay", IEEE, 1996.

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