System for stressing a memory integrated circuit die

Details System for stressing a memory integrated circuit die System for stressing a memory integrated circuit die

1997-08-21

1999-04-27

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365149, G11C 700

Patent

active

058986294

ABSTRACT:
A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

REFERENCES:
patent: 5294776 (1994-03-01), Furuyama
patent: 5298433 (1994-03-01), Furuyama

Affiliated with

Also associated with

Rating

System for stressing a memory integrated circuit die does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for stressing a memory integrated circuit die, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for stressing a memory integrated circuit die will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-689828