Semiconductor memory having redundant memory cell array

Static information storage and retrieval – Read/write circuit – Bad bit

Patent

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Details

36523006, 365201, 36523008, G11C 700

Patent

active

058986278

ABSTRACT:
To make a read/write test on a redundant memory and to realize the detection of faults of the redundant memory cell array in advance, there are provided a first control circuit which inhibits the activation of word lines for selecting a normal memory cell array in response to a test signal and a second control circuit which activates redundant word lines for selecting a redundant memory cell array in response to the test signal.

REFERENCES:
patent: 5349556 (1994-09-01), Lee

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