Memory redundancy circuit using single polysilicon floating gate

Details Memory redundancy circuit using single polysilicon floating gate Memory redundancy circuit using single polysilicon floating gate

1998-09-21

2000-02-29

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 36523006, 36518509, G11C 1606

Patent

active

06031771&

ABSTRACT:
A read-only memory device is provided which comprises an array of read-only memory cells arranged in rows and columns. An additional row or column of flat, single polysilicon floating gate memory cells is provided. A row or column decoder coupled to the array of read-only memory cells is responsive to addresses corresponding to rows or columns in the array for selecting addressed rows or columns. Control circuitry including a programmable store for identifying a defective row or column in the array to be replaced by the additional row or column, selects the additional row or column and replaces the defective row or column in response to an address corresponding to the defective row or column. In addition, circuitry is provided on the integrated circuit which allows access to the additional row or column of floating gate memory cells for programming the additional row or column. The additional row or column of floating gate memory cells is comprised of flat or single polysilicon floating gate cells having buried diffusion control gates. This structure is particularly applied to an array of mask ROM cells. Furthermore, the additional row or column of floating gate memory cells can be implemented in layout of mask ROM cells itself, and a very dense compact structure without requiring additional process steps to implement the redundant row or column.

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