Asynchronous registers with embedded acknowledge collection

Electronic digital logic circuitry – Threshold – With field-effect transistor

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326 59, 326136, 327185, 365 78, H03K 1923, H03K 1900

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active

060313900

ABSTRACT:
An asynchronous register with embedded acknowledge collection is disclosed. The asynchronous register includes a data threshold circuit for generating data or NULL values at an output signal line based upon an evaluation of at least one data input value and an acknowledgment collection circuit, embedded in the data threshold circuit, for collecting a plurality of acknowledge signals and resolving the acknowledge signals for controlling, in combination with the at least one data input value, the passing of the data or NULL values to the output signal line. The acknowledgment collection circuit includes an M of N acknowledge collection circuit, wherein N is an integer representing the number of acknowledge signals being resolved and M representing a threshold, wherein M.ltoreq.N. The M of N acknowledge collection circuit allows the data input values to pass as data to the output signal line after M acknowledge signals assert a request for data and allows the data input values to pass as NULL to the output signal line after P acknowledge signals assert a request for NULL, wherein P.ltoreq.N. P may or may not be equal to M. A reset network is provided for providing system initialization at registration boundaries and is made transparent during normal operating conditions.

REFERENCES:
patent: 3610950 (1971-10-01), Keller et al.
patent: 3715603 (1973-02-01), Lerch
patent: 4845633 (1989-07-01), Furtek
patent: 5121003 (1992-06-01), Williams
patent: 5305463 (1994-04-01), Fant et al.
patent: 5382844 (1995-01-01), Knauer
patent: 5652902 (1997-07-01), Fant
patent: 5656948 (1997-08-01), Sobelman et al.
patent: 5764081 (1998-06-01), Fant et al.
Anantharaman, "A delay insensitive regular expression recognizer," research paper, Dept. of Computer Science, Carnegie-Mellon University, pp. 1-10 (Jan. 1989).
Brzozowski et al., "Asynchronous Circuits," Table of Contents, 20 pgs. (1995).
Burford et al., "An 180 Mhz 16 bit Multiplier Using Asynchronous Logic Design Techniques," IEEE 1994 Custom Integrated Circuits Conference, pp. 215-218 (1994).
Dean, "Strip: A Self-Timed Risk Protector," Dissertation, STRiP's Implementation, Computer Systems Laboratory, Stanford University, pp. 108-114 and 145-147 (Jul. 1992).
Greenstreet et al., "Self-Timed Iteration," Elsevier Science Publishers B.V. (North Holland), pp. 309-322 (1988).
Hampel et al., "Threshold logic," IEEE Spectrum, pp. 32-39 (May 1971).
Heller et al., "Session I: Custom and Semi-Custom Design Techniques --WAM 1.3: Cascode Voltage Switch Logic: A Differential CMOS Logic Family," IEEE International Solid State Circuit Conference, 2 pgs. (1984).
Mead et al., "Introduction to VLSI Systems," Addison-Wesley Series in Computer Science, pp. 242-262 (1980).
Meng et al., "Automatic Synthesis of Asynchronous Circuits from High-Level Specifications," IEEE Transactions on Computer-Aided Design, vol. 8, No. 11, pp. 1185-1205 (Nov. 1989).
Muller, "Asynchronous Logics and Application to Information Processing," Switching Theory in Space Technology, pp. 289-297 (1963).
Nielsen et al., "A low-power Asynchronous Data-path for a FIR filter bank," IEEE, pp. 198-207 (1996).
Renaudin et al., "The Design of Fast Asynchronous Adder Structures and Their Implementation Using D.C.V.S. Logic," International Symposium on Circuits and Systems, vol. 4, pp. 291-294 (undated).
Shibata et al., "A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations," IEEE Transactions on Electron Devices, vol. 39, No. 6, pp. 1444-1455 (Jun. 1992).
Singh, "A Design Methodology for Self-Timed Systems," Thesis, Massachussetts Institute of Technology, pp. 1-98 (Feb. 1981).
Sparso et al., "Design of delay insensitive circuits using multi-ring structures," EURO-DAC '92 European Design Automation Conference, IEEE, pp. 15-20 (1992).
Sparso et al., "Delay-insensitive multi-ring structures," Integration, the VLSI journal 15, pp. 313-340 (1993).
Sutherland, "Micropipelines," Communications of the ACM, vol. 32, No. 6, pp. 720-738 (Jun. 1989).
Unger, "Asynchronous Sequential Switching Circuits," Chapter 6, Department of Electrical Engineering, Columbia University, pp. 221-229 (1969).
Williams, "Latency and Throughput Tradeoffs in Self-Timed Speed-Independent Pipelines and Rings," Technical Report No. CSL-TR-90-431, Computer Systems Laboratory, Stanford University, pp. 1-26 (Aug. 1990).
Williams, "Self-Timed Rings and Their Application to Division / Chapters 1-7," Technical Report No CSL-TR-91-482, Computer Systems Laboratory, Stanford University, pp. 1-144 (May 1991).
Wojcik et al., "On the Design of Three-Valued Asynchronous Modules," IEEE Transactions on Computers, vol. C --29, No. 10, pp. 889-898 (Oct. 1980).
Wuu et al., "Transaction Brief --A Design of a Fast and Area Efficient Multi-Input Muller C-element," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, No. 2, pp. 215-219 (Jun. 1993).

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