Method and apparatus for synthesizing clock signals for use with

Details Method and apparatus for synthesizing clock signals for use with Method and apparatus for synthesizing clock signals for use with

1995-07-07

1997-02-04

Hsu, Alpus H.

Multiplex communications

Communication techniques for information carried in plural...

Adaptive

370474, 370395, 39520013, 39520020, H01J 1300, H04J 306

Patent

active

056006500

ABSTRACT:
An asynchronous transfer mode (ATM) segmentation and reassembly (SAR) chip is provided for interfacing a host computer with an ATM system having a physical layer (PHY) chip incorporating, for example, a Unified Test and Operations Physical Interface for ATM (UTOPIA) protocol. The PHY chip is capable of operating at both 155 Mbps and 622 Mbps data transmission rates. The UTOPIA protocol requires a clock which is provided by the SAR chip. In an exemplary embodiment described herein, the SAR chip is configured to accommodate both data transmission rates and to synthesize appropriate clock signals for driving the PHY chip which facilitate the clocking out of data and the sampling of data.

REFERENCES:
patent: 5375121 (1994-12-01), Nishino et al.
patent: 5418786 (1995-05-01), Loyer et al.
patent: 5485456 (1996-01-01), Shtayer et al.

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