Modifying RAS timing based on wait states to accommodate differe

Details Modifying RAS timing based on wait states to accommodate differe Modifying RAS timing based on wait states to accommodate differe

1997-03-07

1999-04-27

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

365193, 365203, G06F 1200

Patent

active

058976590

ABSTRACT:
A DRAM control circuit accommodates different speed grade DRAMs by modifying the RAS strobe. A number of wait states are inserted into a DRAM access cycle, having a start time and an end time, between the start and the end time of the access cycle. When the number of wait states inserted is zero, the RAS is deasserted at a first time relative to the end of the access cycle. When the number of wait states is at least one, the RAS is deasserted at a second time, earlier than the first time, relative to the end time of the access cycle, thereby increasing the row address strobe precharge time.

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