Serial bus system for shadowing registers

Details Serial bus system for shadowing registers Serial bus system for shadowing registers

1996-07-19

1998-05-05

Harvey, Jack B.

395310, G06F 1300

Patent

active

057489114

ABSTRACT:
A low latency serial bus system for shadowing registers between first and second digital devices. Either the first device or the second device may initiate a data transfer cycle on the serial bus when data in a shadowed register of that device has changed. The data transfer cycle includes a first frame where data is transferred from the first device to the second device and a second frame where data is transferred from the second device to the first device. The devices do not initiate a subsequent data transfer cycle for changed data if the changed data can be transferred in the current data transfer cycle.

REFERENCES:
patent: 5596724 (1997-01-01), Mullins et al.
patent: 5608876 (1997-03-01), Cohen et al.
patent: 5630147 (1997-05-01), Datta et al.
patent: 5642489 (1997-06-01), Bland et al.
patent: 5649127 (1997-07-01), Hang
patent: 5666495 (1997-09-01), Yeh
I.sup.2 C-bus and how to use it, Phillips Semiconductors, 1992.
Serialized IRO Support for PCI Systems, Sep. 1, 1995, Rev. 6.0.
Intel.RTM. System Management Bus Specification, Rev. 1.0, Feb. 15, pp. 1-17, 1995.
Universal Serial Bus Specification, Rev. 0.9, pp. 14-22, pp. 63-80, Apr. 1995.

Affiliated with

Also associated with

Rating

Serial bus system for shadowing registers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Serial bus system for shadowing registers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Serial bus system for shadowing registers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-67396