Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

1997-06-12

2000-08-01

Meier, Stephen D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

060970642

ABSTRACT:
An improvement of a resistance to electrostatic discharge of a semiconductor integrated circuit device is aimed. An IC having a high ESD immunity is realized by causing a surface concentration of N type impurities in a drain area of an N-channel type MOS transistor to be more than 5 E 18/cm.sup.3 in maximum in the direction of gate electrode of a gate electrode terminal and to have a monotonous concentration profile in which there is no kink in a portion less than 5 E 18/cm.sup.3 in the surface direction.

REFERENCES:
patent: 4691217 (1987-09-01), Ueno et al.
Patent Abstracts of Japan, vol 12, No. 250 (E-633) Jul. 14, 1988.
Patent Abstracts of Japan, vol 10, No. 306 (E-446) Oct. 17, 1986.
Patent Abstracts of Japan, vol. 17, No. 549 (E-1443) Oct. 4, 1993.
Patent Abstracts of Japan, vol. 17, No. 440 (E-1414) Aug. 13, 1993.
IEEE Electronic Device Letters, vol. 14, No. 7, Jul. 1993, New York, USA, pp. 326-328, Keon Verhaege et al., "Double Snapback in SOI nMOSFET's and its Application for SOI ESD Protection".
Electrical Overstress/Electrostatic Discharge Symposium Proceedings, Anaheim, CA, USA, Sep. 27-29, 1988, C. Duvvury et al., "Output ESD Protection Techniques for Advanced CMOS Processes".
Sze, Semiconductor Devices, Physics & Tech, pp. 218, 219, 394-397, and 401, .COPYRGT.1985.

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