Transistor, transistor array, method for manufacturing transisto

Details Transistor, transistor array, method for manufacturing transisto Transistor, transistor array, method for manufacturing transisto

1997-12-23

2000-08-01

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257316, 257319, H01L 29788

Patent

active

060970596

ABSTRACT:
A memory cell including source-drain regions, a channel region, floating gate electrodes, and a control gate electrode. The floating gate electrodes are placed next to each other over the channel region on a gate insulating layer. The control gate electrode is located over the floating gate electrodes on an insulating layer and an insulating layer, both layers being formed by a LOCOS method. Protuberances are formed on the upper corners of the floating gate electrodes by the insulating layer. A central portion of the control gate electrode is laid over the channel region on insulating layers, to form a selecting gate. A selecting transistor comprises this selecting gate between both the source-drain regions.

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Montalvo, A.J., et al, "Improved Floating-Gate Devices Using Standard CMOS Technology," IEEE Electron Device Letters, vol. 24, No. 8, Aug. 1, 1993.
Silicon Processing for the VLSI Era, vol. 1: Process Technology, S. Wolf et al., p. 191, 1986.
Microelectronic Processing, An Introduction to the Manufacture of Integrated Circuits, W. Ruska, p. 92, 1987.
Principles of Electronic Circuits, Burns et al., p. 231, 1987.

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