Programmable logic device with fixed and programmable memory

Details Programmable logic device with fixed and programmable memory Programmable logic device with fixed and programmable memory

1996-10-11

1998-02-03

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, H03K 19177

Patent

active

057148902

ABSTRACT:
An improved programmable logic device (PLD) comprises a programmable AND first array to which a set of PLD input lines are selectively connectable and providing a set of outputs which are selectively connectable to a set of inputs to a programmable OR second army which drives a second set of output lines, in combination with a programmable AND third array having a set of inputs that are selectively connectable to the set of input lines and having a set of outputs that are fixedly connected as a set of inputs to a fixed OR fourth array providing a set of PLD outputs, with the set of outputs from the OR second array also connected in a fixed manner as inputs to the OR fourth array. This arrangement overcomes some of the weaknesses in both the conventional PAL and PLA architectures while retaining most of their strengths.

REFERENCES:
patent: 4422072 (1983-12-01), Cavlan
patent: 4758746 (1988-07-01), Birkner et al.
patent: 4942319 (1990-07-01), Pickett et al.
patent: 5189320 (1993-02-01), Gongwer
patent: 5235221 (1993-08-01), Douglas et al.
patent: 5260610 (1993-11-01), Pedersen et al.
Weste et al.; "Principles of CMOS VLSI Design, A Systems Perspective"; .COPYRGT. 1985 by AT&T Bell Laboratories, Inc. and Kamran Eshraghian; pp. 180-183.

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