Electrostatic discharge protection device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257401, H01L 2362, H01L 2976

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active

057147841

ABSTRACT:
The present invention is an electronic device, and more particularly an MOS transistor. A square-type layout style is used to realize the MOS device. By using the present layout style, the output driving/sinking capability of output buffers as well as the ESD protection capability of NMOS and PMOS devices in output buffers or input ESD protection circuits are significantly improved within smaller layout area. Both drain diffusion area and drain-to-bulk parasitic capacitance at the output node are reduced by this square-type layout. Devices using the present layout style can be assembled to form larger, rectangular (or square) and similarly functioning devices. Thus, the present square-type layout style is very attractive to submicron CMOS VLSI/ULSI in high-density and high-speed applications.

REFERENCES:
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patent: 5272371 (1993-12-01), Bishop et al.
patent: 5404041 (1995-04-01), Diaz et al.
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C. H. Diaz, T.E. Kopley and P.J. Marcoux, "Building-in ESD/EOS reliability for sub-halfmicron CMOS Processes", Proc. of IRPS, pp. 276-283, 1995.
L. Baker, R. Currence, S. Law, M. Le, S.T. Lin, and M. Teene, "A waffle layout technique strengthens the ESD hardness of the NMOS output transistor", EOS/ESD Symp. Proc., EOS-11, pp. 175-181, 1989.
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S. Daniel and G. Krieger, "Process and design optimization for advanced CMOS I/O ESD protection devices", EOS/ESD Symp. Proc., EOS-12, pp. 206-213, 1990.

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