Fabrication method of semiconductor device using CMP process

Details Fabrication method of semiconductor device using CMP process Fabrication method of semiconductor device using CMP process

1998-04-10

2000-08-01

Everhart, Caridad

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438633, 438692, 438693, H01L 214763

Patent

active

060966327

ABSTRACT:
A fabrication method of a semiconductor device is provided, which eliminates the effects of polishing residue generated by a CMP process. A first layer having a hole is prepared, where the first layer may be formed directly on a surface of a semiconductor substrate or formed over a surface of a semiconductor substrate through at least one layer. A second layer is then formed to cover the hole. The hole is not filled with the second layer to thereby form a gap on the second layer. A protection layer is formed on the second layer so that the gap is filled with the protection layer. The protection layer and the second layer are removed by a CMP process until the first layer is exposed, thereby selectively leaving the protection layer and the second layer in the hole. The second layer left in the hole serves as a plug. A third layer is formed on the second layer to cover the plug. Preferably, a step of selectively removing the protection layer left in the gap is additionally provided prior to the CMP process.

REFERENCES:
patent: 5300813 (1994-04-01), Joshi et al.
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5658830 (1997-08-01), Jeng
patent: 6960314 (1999-09-01), Rhodes et al.
Chris Yu et al., "Improved Multilevel Metallization Technology Using Chemical Mechanical Polishing of W Plugs and Interconnects", Proceeding of VLSI Multilevel Inter Connection Conference (VMIC), Jun. 7-8, 1994, pp. 144-150.

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