Optimizing data movement with hardware operations

Details Optimizing data movement with hardware operations Optimizing data movement with hardware operations

1997-06-24

1999-10-12

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

711156, 711171, 711172, 711173, G06F 1200

Patent

active

059667338

ABSTRACT:
In a computer system, an architecture for optimizing aspects of data movement operations by performing functions such as memory allocation and notification on hardware rather than software. The invention thereby optimizes several higher-level processor operations that involve data movement, including internodal messaging, data copying, and data zeroing. Method and apparatus is also disclosed for detecting and responding to translation lookaside buffer (TLB) purges indicating a change in physical memory mapping during translation of virtual memory to physical memory.

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patent: 5581737 (1996-12-01), Dahlen et al.
patent: 5715430 (1998-02-01), Hirayama

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