Method of forming dual field isolation structures

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation

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438225, 438297, 257509, 257647, H01L 2176

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active

059666188

ABSTRACT:
A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.

REFERENCES:
patent: 5110756 (1992-05-01), Gregor et al.
patent: 5128274 (1992-07-01), Yabu et al.
patent: 5316966 (1994-05-01), Van Der Plas et al.
patent: 5466623 (1995-11-01), Shimizu et al.
patent: 5646063 (1997-07-01), Mehta et al.
patent: 5786264 (1998-07-01), Hwang
patent: 5794809 (1998-08-01), Gardner et al.

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