Semiconductor device with vertical transistors connected in seri

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257302, 257401, H01L 2926

Patent

active

054163501

ABSTRACT:
A semiconductor device connected between first and second wiring lines comprises a semiconductor substrate, a first semiconductor column formed by etching the substrate by a predetermined depth, a second semiconductor column formed by etching the substrate by a predetermined depth, with a predetermined distance set from the first semiconductor column, a first gate electrode formed around a side wall of the first semiconductor column with an insulating layer interposed, a second gate electrode formed around a side wall of the second semiconductor column with an insulating layer interposed, a first diffusion layer functioning as one of a source and a drain, the first diffusion layer being formed at a top portion of the first semiconductor column and connected to the first wiring line, a second diffusion layer functioning as another of the source and the drain, the second diffusion layer being formed at a top portion of the second semiconductor column and connected to the second wiring line, and a diffusion layer functioning as one of a source and a drain, the diffusion layer being formed at bottom portions and peripheral portions of the bottom portions of the first and second semiconductor columns and shared by the first and second semiconductor columns.

REFERENCES:
patent: 4630088 (1986-12-01), Ogura et al.
patent: 5258635 (1993-11-01), Nitayama et al.
patent: 5276343 (1994-01-01), Kumagai et al.
H. Takato, et al., "Impact of Surrounding Gate Transistor (SGT) for Ultra-High Density LSI's, IEE Transactions on Electron Devices", vol. 38, No. 3, Mar. 1991, pp. 573-578.

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