Non-volatile memory having a cell applying to multi-bit data by

Details Non-volatile memory having a cell applying to multi-bit data by Non-volatile memory having a cell applying to multi-bit data by

1995-11-21

1998-04-14

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257319, 36518526, H01L 29788

Patent

active

057395683

ABSTRACT:
An object of the present invention is to contribute to increase of storage capacity of a memory. A non-volatile memory having a cell applying to multi-bit data by double layered floating gate architecture. The memory has a storage cell transistor which comprises source 2 and drain 3 being formed in a semiconductor substrate 1 distantly from each other. The storage cell transistor, furthermore comprises a single first floating gate 4A being laid between the source and drain above the semiconductor substrate, and a plurality of second floating gates 4B.sub.1 -4B.sub.n which are distant from each other and face the first floating gate. Since the second floating gates respectively store carrier corresponding to data bits and the first floating gate determines a threshold value of drain current in accordance with sum amount of carrier stored in all of the second floating gates, two or more bits data can be saved per one storage cell.

REFERENCES:
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patent: 4503519 (1985-03-01), Arakana
patent: 5252847 (1993-10-01), Arima et al.
patent: 5569946 (1996-10-01), Hong
A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations, Shibata et al, IEE Transactions on Electron Devices, vol. 39, No. 6, Jun. 1992, pp. 1444-1455.
Complete Transient Simulation of Flash EEPROM Devices, Keeney et al, IEE Transactions on Electron Devices, vol. 39, No. 12, Dec. 1992, p. 2750-2757 .

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