Semiconductor memory device having a redundant row and a redunda

Details Semiconductor memory device having a redundant row and a redunda Semiconductor memory device having a redundant row and a redunda

1996-03-27

1997-07-29

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, G11C 700

Patent

active

056527250

ABSTRACT:
A semiconductor memory device includes a memory cell array, a redundant row memory cell array, a redundant column memory cell array and a redundant column row memory cell array. A redundant row test activation signal, a redundant column test activation signal and a multi-bit test activation signal are activated in response to signals RAS, CAS and WE and address key signals. In a redundant row test mode, a redundant word line is selectively driven in response to a row address signal. In a row column test mode, a redundant column selection line is selectively driven in response to a column address signal. In addition, data shrinking circuit is provided in order to enable a multi-bit test of redundant rows and redundant columns.

REFERENCES:
patent: 4860260 (1989-08-01), Saito et al.
patent: 5206831 (1993-04-01), Wakamatsu
patent: 5400290 (1995-03-01), Suma et al.
"A 90ns 1Mb DRAM with Multi-Bit Test Mode" by Kumanoya et al., IEEE International Solid-State Circuits Conference 1985, pp. 240-241.

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