Method and apparatus for reducing clock-data skew by clock shift

Details Method and apparatus for reducing clock-data skew by clock shift Method and apparatus for reducing clock-data skew by clock shift

1995-09-29

1997-07-29

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

H03K 19096

Patent

active

056525303

ABSTRACT:
A data signal is input into an integrated circuit and the data signal is transmitted through a series of logic gates that cause a propagation delay. An external clock line associated with the data signal is also inputted into the integrated circuit. The external clock signal is passed through a delay shifter that adds a controllable amount of delay to the clock signal. The amount of delay added to the clock signal should equal the total amount of propagation delay added to the data signal. The clock signal is then also transmitted through a phase-lock loop to stabilize the clock signal. The delayed internal clock signal is then used to clock the data signal which has been transmitted through a series of logic gates that have added propagation delay. Since the internal clock signal has been delayed an equal amount as the data signal, the data signal will be clocked at an appropriate time.

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