Synchronization circuit for a Viterbi decoder

Details Synchronization circuit for a Viterbi decoder Synchronization circuit for a Viterbi decoder

1983-07-06

1986-03-25

Orsino, Jr., Joseph A.

Pulse or digital communications

Spread spectrum

Direct sequence

371 46, 375118, H04L 704

Patent

active

045788006

ABSTRACT:
A Viterbi decoder synchronization circuit comprises a phase shifter for introducing a variable amount of delay time to a received bit stream of convolutional codes in response to a control signal applied thereto with respect to a word synchronization signal which is derived from the bit stream. A first detector detects maximum and minimum metric values of the Viterbi decoder. A second detector detects the difference between the detected maximum and minimum metric values for coupling to an integrator. The output of the integrator is applied to a third detector which detects when the integrator output reaches a value indicative of a word-in-sync or word-out-of-sync condition. A phase shift signal is generated in response to an output signal from the third detector and applied to the phase shifter as the control signal.

REFERENCES:
patent: 3789359 (1974-01-01), Clark, Jr. et al.
patent: 3872432 (1975-03-01), Bismarck

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