Asynchronous memory refresh arbitration circuit

Static information storage and retrieval – Read/write circuit – Data refresh

Patent

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Details

364900, G11C 700, G06F 946

Patent

active

045787824

ABSTRACT:
An arbitration circuit for asynchronously arbitrating between refreshing memory and performing a non-refresh memory cycle in a memory system having memory cycle generating circuitry. Arbitration circuitry comprising logic circuitry, a clocked storage device and delay circuits which are coupled to memory cycle generating circuitry for performing an arbitration decision for a memory during an immediately preceding memory cycle. The arbitration circuitry time overlaps an arbitration operation with a memory cycle operation during a first memory cycle, thereby improving data rate for an adjacent second memory cycle.

REFERENCES:
patent: 4339808 (1982-07-01), North
patent: 4406013 (1983-09-01), Reese et al.

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