Nonvolatile semiconductor memory device having a row decoder sup

Details Nonvolatile semiconductor memory device having a row decoder sup Nonvolatile semiconductor memory device having a row decoder sup

1994-12-19

1996-04-30

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, 36518911, 36523006, 36518518, 36518512, 326108, 327534, G11C 800

Patent

active

055131468

ABSTRACT:
A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.

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