Circuit for high speed serial programming of programmable logic

Static information storage and retrieval – Addressing – Sync/clocking

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Details

36518912, 365236, 365239, 365240, G11C 800

Patent

active

057485593

ABSTRACT:
The present invention provides a circuit for programming a logic device comprising a first register for shifting data to a memory array, a second register for decoding an address space for a particular word within the logic device. The memory array has an address input and a data input coupled to the first and second registers. One of the registers is implemented as a registered counter block while the other register can be implemented as either a shift register, for a low pin count design, and/or a parallel load register for a higher pin counter and higher performance design.

REFERENCES:
patent: 4773049 (1988-09-01), Takemae
patent: 5432747 (1995-07-01), Fuller et al.
patent: 5487049 (1996-01-01), Hang

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