Non-voltile memory device, non-volatile memory cell and method o

Details Non-voltile memory device, non-volatile memory cell and method o Non-voltile memory device, non-volatile memory cell and method o

1994-12-20

1998-05-05

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular biasing

36518519, 36518529, G11C 1134

Patent

active

057485305

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device which can electrically rewrite information or data, and more particularly to a non-volatile semiconductor memory device which can simply and surely perform write and erase operations.
2. Description of the Prior Art
In conventional non-volatile semiconductor memory devices, the operation of rewriting stored data can be classified into (1) a system of write by hot-electrons and erase by tunnelling currents and (2) a system of write and erase by tunnelling currents.
The former rewrite system is directed to an electrical erasing type flash EEPROM. The write operation is made as follows. A write voltage Vpp is applied to both control gate and drain of a memory cell to inject hot electrons into the floating gate. Therefore, the threshold voltage Vth for in the memory cell depends on the channel length, the thickness of a tunnelling insulating film and a source-drain voltage. This results in a wide distribution of the threshold voltages Vth after write in memory cells as shown in FIGS. 38A and 38B.
The erase operation is made as follows. With the control gate connected to ground, an erase voltage Vpp is applied to a source (or drain) electrode of the memory cell to extract the electrons trapped in the floating gate into the source (or drain) electrode. As in the write operation, in the erase operation also, the threshold voltage depends on the voltage on a word line, the drain voltage and the tunnelling insulating film thickness. This results in a wide distribution of the threshold voltages Vth after erase in memory cells as shown in FIGS. 38A and 38B.
The latter rewrite system is directed to an NAND type EEPROM. In this non-volatile memory, the write and erase operations are performed using the tunnelling current from the entire floating gate. As in the above erase operation, the threshold value Vth depends on the voltage on a word line, the drain voltage and the tunnelling insulating film thickness. This results in a wide distribution of the threshold voltages Vth after write and erase in memory cells as shown in FIG. 38C.
Incidentally, FIG. 38D shows the distribution of threshold voltages Vth in an ultra-violet erasing type UVEPROM. The write operation is performed in such a manner that a write voltage Vpp is applied to both control gate and drain electrode of a memory cell to inject hot-electrons into the floating gate. This results in a wide distribution of the threshold voltages Vth after write in the memory cells as in the flash EEPROM. On the other hand, the erase operation is performed in such a manner that the electrons trapped in the floating gate are extracted by irradiation of ultra-violet rays. This results in a sharp distribution of the threshold voltages Vth in the neighborhood of 0.8 V after erase in the memory cells. In FIGS. 38A to 38D showing the distributions of threshold voltages, it should be noted that the ordinate denotes a threshold voltage Vth in a memory cell and the abscissa denotes its frequency thereof, and noted that the state with charges stored in a floating gate is referred to as "0" data whereas the state with no charges stored in the floating gate is referred as to "1" data.
As described above, the conventional non-volatile semiconductor memories are characterized by a relatively wide distribution of threshold voltages Vth. Therefore, the write and erase operations cannot be executed with the same threshold voltage Vth set. The threshold voltages fluctuate in the same memory chip also. So, generally, the write time is changed for each bit so that the threshold volatges are placed in a predetermined range. This takes a relatively long write time.
Further, the conventional non-volatile semiconductor memories are provided with a logic circuit for detecting the write state or erasure state of a memory cell and modifying it. The logic circuit occupies a larger area in a semiconductor memory device. In many cases, the logic circuit detects the write or

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