Control circuit for a semiconductor memory device and semiconduc

Details Control circuit for a semiconductor memory device and semiconduc Control circuit for a semiconductor memory device and semiconduc

1989-08-15

1991-07-09

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

Signals

365194, 36518901, 365233, G11C 700, G11C 11413

Patent

active

050311506

ABSTRACT:
A control circuit for a dynamic memory device comprises first timer means for delaying the Row Address Stroke (RAS) signal by a first delay time and supplying the delayed RAS signal to a row control circuit, and a second timer means for delaying the RAS signal by a second delay time and supplying this delayed RAS signal to a column control circuit.

REFERENCES:
patent: 4575825 (1986-03-01), Ozaki
patent: 4596004 (1986-06-01), Kaufman
patent: 4656612 (1987-04-01), Allan
patent: 4809230 (1989-02-01), Konishi et al.
patent: 4823322 (1989-04-01), Miyatake et al.
patent: 4866675 (1989-09-01), Kawashima

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