Method of forming substantially planar digit lines

Details Method of forming substantially planar digit lines Method of forming substantially planar digit lines

1990-06-05

1991-07-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437190, 437193, 437195, 437228, H01L 2170

Patent

active

050305875

ABSTRACT:
A method of forming digit lines on a semiconductor wafer having integrated circuits comprises the following consecutive steps:

REFERENCES:
patent: 4829025 (1989-05-01), Iranmanesh
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 4868138 (1989-09-01), Chan et al.
patent: 4871688 (1989-10-01), Lowrey
patent: 4957881 (1990-09-01), Crotti
patent: 4961822 (1990-10-01), Liao et al.
Shibata et al., "High Performance Half-Micron PMOSFETs with 0.1 .mu.m Shallow p+n Junction Utilizing Selected Silicon Growth and Rapid Thermal Annealing", IEDM, 1987, pp. 590-593.
S Wolf and RN Tauber, "Silicon Processing from the VLSI Era", vol. 1, Lattice Press, Sunset Beach, 1986, p. 124.

Affiliated with

Also associated with

Rating

Method of forming substantially planar digit lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming substantially planar digit lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming substantially planar digit lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-618013