Bus arbiter provided in a multi-processor system

Details Bus arbiter provided in a multi-processor system Bus arbiter provided in a multi-processor system

1994-03-18

1998-03-31

Harvey, Jack B.

G06F 1300

Patent

active

057348456

ABSTRACT:
In a multi-processor system in which a plurality of units such as a CPU serving as an information processing unit and an I/O control unit can be connected over a system bus, when the plurality of units issue use requests for the system bus, a bus arbiter grants a use authority for the system bus to a specific unit in consideration with priority orders. The bus arbiter is connected to the respective units over at least one specific signal line. The specific signal line conforms to a specific transmission rule in a normal control mode, whereby a specific signal is transmitted over the specific signal line. When a unit is not connected, at least one specific signal line in the bus arbiter is fixed to a state unfeasible in a normal control mode. The specific signal line is monitored if necessary. When the specific signal line linked with a unit is controlled under a specific transmission rule, the unit is recognized as connected. When the specific signal line is fixed to a state unfeasible in a normal control mode, the unit is recognized as unconnected. This obviates the necessity of increasing the number of buses, allows the bus arbiter to distinguish units connected over the system bus from unconnected ones, and realizes a small-sized system.

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patent: 5287531 (1994-02-01), Rogers, Jr. et al.
patent: 5548782 (1996-08-01), Michael et al.

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