Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1987-03-02
1988-02-23
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
371 10, G11C 1140
Patent
active
047275162
ABSTRACT:
The semiconductor memory device includes at least two memory arrays, a first selection circuit which selects a memory cell from either one of the memory arrays in accordance with address signals, preferably two spare memory arrays and a second selection circuit which selects a memory cell from either one of the spare memory arrays. If a defective memory cell or cells are contained in one of the two memory arrays, the second selection circuit can select a spare memory cell or cells from any of the two spare memory arrays in place of the defective memory cell or cells. Thus, the spare memory arrays can be used effectively. Two sets of main amplifiers are also disposed and only one of them, which receives the data from the memory cell selected from the memory arrays or spare memory arrays, is operated. Thus, lower power consumption can be realized.
REFERENCES:
patent: 4459685 (1984-07-01), Sud et al.
B. F. Fitzgerald et al., "Memory System with High-Performance Word Redundancy", IBM Technical Disclosure Bulletin, vol. 19, No. 5, Oct. 1976, pp. 1638-1639.
Patent Abstracts of Japan, vol. 6, No. 38, p. 105[916], Mar. 9, 1982, "Defective Bit Relief Circuit".
Oishi Kanji
Yoshida Masahiro
Hitachi , Ltd.
Popek Joseph A.
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