Dynamic random access memory having improved refresh timing

Details Dynamic random access memory having improved refresh timing Dynamic random access memory having improved refresh timing

1989-12-14

1991-01-15

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

36523008, 365233, 365193, G11L 700

Patent

active

049858688

ABSTRACT:
A dynamic random access memory including: a memory constituted by a plurality of dynamic type memory cells; a refresh control circuit for refreshing the memory cells by controlling a refresh address circuit in a refresh mode; an address latch circuit for latching an external address signal in a read/write mode and latching a refresh address signal in the refresh mode; a clock generating circuit for generating a second clock and a third clock based on a first clock obtained after a predetermined delay time from a trailing edge of a row address strobe signal, the second clock controlling a first timing for taking the external address signal into the address latch circuit in the read/write mode, and the third clock is generated after the second clock and controls a second timing for taking the refresh address signal into the address latch circuit in the refresh mode.

REFERENCES:
patent: 4334295 (1982-06-01), Nagami
patent: 4472647 (1984-09-01), Allgood et al.
patent: 4672243 (1987-06-01), Kirsch
patent: 4682052 (1987-07-01), Kyomasu
patent: 4747082 (1988-05-01), Minato et al.
patent: 4758992 (1988-07-01), Taguchi
Soviet Invetions Illustrated, Section E1, Week 8341, Nov. 23, 1983, Su-982 089.

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