Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Patent
1998-01-29
2000-08-22
Ellis, Richard L.
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
712228, G06F 900
Patent
active
061087718
ABSTRACT:
A system and method for register renaming and allocation in an out-of-order processing system which allows the use of a minimum number of physical registers is described. A link list allows concatenation of a physical register representing a certain instance of the corresponding logical register to the physical register representing the next instance of the same logical register. By adding and removing links in this link list, it is possible to manage the assignment of physical registers to logical registers dynamically. Both the physical registers representing speculative instances and the physical registers representing in-order instances are administrated together. This is done by means of an in-order list, which indicates the physical registers that actually represent the architected state of the machine.
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patent: 4511964 (1985-04-01), Georg et al.
patent: 4612612 (1986-09-01), Woffinden et al.
patent: 4638426 (1987-01-01), Chang et al.
patent: 5828903 (1998-10-01), Sethuram et al.
patent: 5872949 (1999-02-01), Kikuta et al.
Gaertner Ute
Getzlaff Klaus Jorg
Pfeffer Erwin
Tast Hans-Werner
Ehrlich Marc A.
Ellis Richard L.
International Business Machines - Corporation
Patel Gautam R.
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