Multiple masters in a memory control system

Details Multiple masters in a memory control system Multiple masters in a memory control system

1997-08-29

2000-08-22

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711105, G06F 1316

Patent

active

061087580

ABSTRACT:
A method and apparatus for multiple masters for a memory control system is provided. The memory control system includes a first master, and a memory coupled to the first master using a memory channel. A second master is coupled between the first master and the memory. The second master writes to and reads from the memory using a transmission reflection from the first master.

REFERENCES:
patent: 5369617 (1994-11-01), Munson
patent: 5390308 (1995-02-01), Ware et al.
patent: 5799209 (1998-08-01), Chatter
Frederick A. Ware, "Rambus Memory Controller", Rambus Inc. documentation, Oct. 15, 1996, pp. 1-20.
"64-Megabit Rambus DRAM Technology Directions", Rambus Inc. documentation, Sep. 10, 1995, pp. 3-24.
"Rambus Memory: Enabling Technology for PC Graphics", Rambus Inc. documentation, Oct. 1994, pp. 1-15.
"Rambus Memory: Multi-Gigabytes/Second And Minimum System Cost", Rambus Inc. documentation, 4 pages.
"Rambus Graphics Roadmap", Rambus Inc. documentation, pp. 1-4.

Affiliated with

Also associated with

Rating

Multiple masters in a memory control system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple masters in a memory control system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple masters in a memory control system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-594947