Method and apparatus for reducing latency of inter-reference ord

Details Method and apparatus for reducing latency of inter-reference ord Method and apparatus for reducing latency of inter-reference ord

1997-10-24

2000-08-22

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

709213, 711147, G06F 1200

Patent

active

061087378

ABSTRACT:
A mechanism reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory. The mechanism comprises a commit-signal that is generated by control logic of the multiprocessor system in response to an issued memory reference operation. The commit-signal facilitates inter-reference ordering; moreover, the commit signal indicates the apparent completion of the memory reference operation, rather than actual completion of the operation. The apparent completion of an operation occurs substantially sooner than the actual completion of an operation, thereby improving performance of the multiprocessor system.

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Shared Memory Consistency Models: A Tutorial, Sarita V. Adve, et al., Western Research Laboratory, 1995, pp. 1-28.

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