Semiconductor memory including a selectively disabled redunancy

Details Semiconductor memory including a selectively disabled redunancy Semiconductor memory including a selectively disabled redunancy

1986-08-07

1989-05-02

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

371 10, G11C 700, G11C 2900

Patent

active

048274526

ABSTRACT:
A semiconductor memory device comprises a main memory 101 and a spare memory 102. When a part of the memory cells of the main memory 101 are defective, these defective memory cells are replaced by memory cells in the spare memory 102. The space memory 102 is decoded by the decoder circuit 104. The decoder circuit 104 is capable of decoding the spare memory 102 using a signal of an instruction memory 107. The instruction memory 107 is selectively enabled or disabled by an instruction control circuit 108. Consequently, in a state in which the instruction memory 107 is disabled by the control circuit 108, a spare memory selection signal is not provided from the instruction memory 107 to the decoder circuit 104 and the semiconductor memory device normally decodes the main memory including defective memory cells. As a result, the addresses and the like of the defective memory cells can be determined.

REFERENCES:
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patent: 4556975 (1985-12-01), Smith et al.
patent: 4667288 (1987-05-01), Keeley et al.
patent: 4714839 (1987-12-01), Chung
Woods, "An E-PROM'S Integrity Starts with its Cell Structure", published in Electronics, Aug. 14, 1980, pp. 132-136.

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