Digital PLL circuit

Details Digital PLL circuit Digital PLL circuit

1996-06-18

1998-05-05

Callahan, Timothy P.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 14, 331 25, H03L 706, H03L 708

Patent

active

057480451

ABSTRACT:
Disclosed is a digital PLL circuit which can permit voltage level conversion using pulse width modulation by a PWM circuit to thereby ensure lower consumed power and a lower implementation density even when the transitional change of the phase error signal is not constant. A phase error signal is obtained based on sample values acquired by sampling a read signal read from a recording medium, and an average phase error signal corresponding to the average value of this phase error signal is obtained. Then, this average phase error signal is sampled and held at a predetermined clock timing to acquire a sampled average phase error signal which is in turn subjected to pulse width modulation for each mentioned predetermined clock timing. A clock signal whose oscillation frequency corresponds to the average voltage level of the resultant pulse width modulation signal is produced as the aforementioned reproduction clock signal.

REFERENCES:
patent: 5325093 (1994-06-01), Takamhori
patent: 5373258 (1994-12-01), Gerot et al.

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