MOS transistor with low-k spacer to suppress capacitive coupling

Details MOS transistor with low-k spacer to suppress capacitive coupling MOS transistor with low-k spacer to suppress capacitive coupling

1998-09-10

2000-08-22

Tran, Minh Loan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257382, 257410, 257900, H01L 2976, H01L 2994, H01L 31062, H01L 27088, H01L 27095

Patent

active

061076678

ABSTRACT:
A method for making a ULSI MOSFET includes establishing a void in a field oxide layer on a silicon substrate and filling the center of the void with a gate electrode. A high-k gate insulator is sandwiched between the gate electrode and the substrate. Around the void, a low-k gate spacer is formed, with the gate spacer being disposed directly above the source and drain extensions of the MOSFET.

REFERENCES:
patent: 5134451 (1992-07-01), Katoh
patent: 5292673 (1994-03-01), Shinriki et al.
patent: 5376578 (1994-12-01), Hsu et al.
patent: 5554544 (1996-09-01), Hsu
patent: 5559049 (1996-09-01), Cho
patent: 5731239 (1998-03-01), Wong et al.
patent: 5734185 (1998-03-01), Iguchi et al.
patent: 5811864 (1998-09-01), Butler

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