Phase lock loop with error consistency detector

Details Phase lock loop with error consistency detector Phase lock loop with error consistency detector

1995-09-28

1996-11-12

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

With intermittent comparison controls

331 1A, 331 17, 331 23, 331DIG2, 327157, 327159, 348540, H03L 7087

Patent

active

055744079

DESCRIPTION:

BRIEF SUMMARY
The invention relates to an arrangement for generating a clock signal.
Digital video signal processing systems with features such as on-screen display of text and picture-in-picture for both television receiver and video tape recorder signal sources may require a clock signal that is phase locked to a horizontal synchronization signal, referred to as line-locked clock. It may be advantageous to form a phase-locked loop (PLL) system for line-locked clock generation for use as a building block in large scale CMOS video signal processing integrated circuits. In such PLL, it may be desirable to have, for example, a clock frequency that ranges from 25 MHz to 40 MHz with a jitter that is less than 2 nS. For such PLL it may be desirable to utilize only one pin for off-chip components. It may also be desirable to use the PLL system with each of the NTSC, PAL and SECAM systems.
It may also be advantageous to operate the PLL with an input sync signal encountered in low-cost consumer video tape recorders without time-base correction, where the horizontal sync can periodically make large phase changes such that the clock signal tracks such sync signal. It may be further desirable to rapidly reduce phase and frequency errors and minimize overshoot and jitter as the PLL settles into phase lock. In addition, it may be desirable to have the PLL discriminate between true output clock phase/frequency errors and those arising from contamination of the input horizontal sync signal with noise bursts or occasional missing pulses.
A PLL system, embodying an inventive feature, utilizes both digital and analog control of an R-C Voltage-Controlled Oscillator to acquire and maintain phase lock of an output clock with respect to an input horizontal sync signal. Depending on the magnitude and consistency of the output clock phase and frequency error, the system automatically selects one of, for example, five control modes of operation of varying sensitivity. The control modes of operation are such that large errors result in large, coarse corrective actions, and small errors result in small, or fine corrective actions.
In a PLL, embodying a different inventive feature, an error in a phase between a horizontal synchronization signal and an output signal of the oscillator is measured. When the phase error exceeds a first predetermined magnitude and provided that a difference between the phase error measured in each of a pair of horizontal line periods is smaller than a second predetermined magnitude, the phase error is corrected in a coarse phase error correction mode. The phase error difference that is smaller than the second predetermined magnitude is indicative of phase error consistency. On the other hand, when the phase error is inconsistent in the pair of periods, the phase error is not corrected and the PLL operates in an idle mode of operation. Advantageously, by disabling the correction of the phase error when the phase error is inconsistent, an occasional noise in the synchronization signal is prevented from disturbing the steady state mode of operation. In this way, noise immunity is increased.
Similarly, when a difference between a frequency error measured in each of a pair of horizontal line periods is larger than a predetermined magnitude that is indicative of inconsistent frequency error, the frequency error is not corrected and the PLL operates in an idle mode of operation. Advantageously, by disabling the correction of the frequency error when the frequency error is inconsistent, noise immunity is increased.
An apparatus, embodying an aspect of the invention, for generating an oscillatory signal includes a controllable oscillator. A first signal that is indicative of one of a frequency and a phase error between the oscillatory signal and a synchronizing signal is provided. The first signal is coupled to a control input of the oscillator for correcting the oscillatory signal to correct for the error in a negative feedback loop manner. The error that is measured in a given pair of periods of the synchronizing signal is co

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