ECL integrated circuit allowing fast operation

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Bipolar transistor

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326 18, H03K 19086

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active

055743919

ABSTRACT:
In an ECL circuit, when a potential of an input signal A changes from "L" to "H", an output signal D correspondingly changes from "H" to "L", and, at this time, an output sent from a switching stage circuit is supplied to a gate of a PMOS transistor via a control capacitor. Thereby, a base current of a pull-down transistor flows, and change of a potential of an output terminal node is promoted. An NMOS transistor receiving the potential of the output terminal node is arranged between a node and a VEE supply terminal. Therefore, when the potential changes, the current flowing through a transistor decreases, and the base current of the pull-down transistor further increases, so that the change of the output signal D is further promoted.

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patent: 5089724 (1992-02-01), Chuang et al.
patent: 5124581 (1992-06-01), Umeki
patent: 5146116 (1992-09-01), Sugimoto
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patent: 5298802 (1994-03-01), Usami et al.
patent: 5321321 (1994-06-01), Kuriu
"A 23-PS/2.1-MW ECL Gate with an AC-Coupled Active Pull-Down Emitter-Follower Stage", Kai-Yap TOH et al, IEEE J. Solid-State Circuits, vol. 24, No. 5, Oct. 1989.

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