Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-06-30
2000-01-18
Chaudhuri, Olik
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438674, 438678, 438682, H01L 21283, H01L 21288
Patent
active
060157526
ABSTRACT:
Low resistivity metal silicide layers are formed on crystalline source/drain regions and polycrystalline gate electrodes with virtually no consumption of crystalline or polycrystalline silicon, thereby reducing parasitic series resistance without encountering junction leakage. Embodiments include selectively depositing a layer of nickel at a temperature less than about 280.degree. C. on the source/drain region and gate electrode, and then depositing a layer of amorphous silicon at a temperature below about 280.degree. C. thereon. An initial low temperature annealing is conducted, e.g., at about 180.degree. C. to about 280.degree. C., to react the amorphous silicon and nickel to form an upwardly grown layer of amorphous nickel silicide on the source/drain region and gate electrode with virtually no consumption of underlying silicon. Unreacted amorphous silicon is then removed, as by wet etching, and a second high temperature annealing is conducted to convert the high resistivity amorphous nickel silicide to low resistivity polycrystalline nickel silicide.
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L.A. Clevenger et al., "Nucleation-limited phase selection during reactions in nickel/amorphous-silicon multilayer thin films", J. Appl. Phys. 67(3), 1990, p. 1325.
Pramanick Shekhar
Xiang Qi
Advanced Micro Devices , Inc.
Chaudhuri Olik
Souw Bernard E.
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