Method of forming salicided self-aligned contact for SRAM cells

Details Method of forming salicided self-aligned contact for SRAM cells Method of forming salicided self-aligned contact for SRAM cells

1996-04-22

1996-11-12

Niebling, John

Fishing, trapping, and vermin destroying

437192, H01L 2128

Patent

active

055739806

ABSTRACT:
This invention provides a method of forming very low resistance self-aligned silicide contacts to devices formed in a silicon integrated circuit substrate while avoiding the formation of stringers or stray silicide conductor paths. The method uses a thin layer of polysilicon which is patterned so as to only cover the contact region of the device being contacted. A layer of metal such as titanium is then deposited and the silicide is formed using rapid thermal annealing. The unreacted metal is then etched away. The primary application is to form a low resistance V.sub.ss plate for adjacent pull down transistors in SRAM cells but can be used in any device requiring a low resistance contact to silicon.

REFERENCES:
patent: 4458410 (1984-07-01), Sugoki et al.
patent: 4966868 (1990-10-01), Muroli et al.
patent: 5045494 (1991-09-01), Choi et al.
patent: 5480814 (1996-01-01), Wuu et al.
"Silicon Processing for the VLSI Era", vol. 2, by S. Wolf, Lattice Press, Sunset Beach, CA, 1990, pp. 144-149.
"VLSI Technology" Second Edition, by S M Sze, McGraw Hill, New York, NY 1988, pp. 397-400 and 479-483.

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