Static semiconductor memory device having test mode

Details Static semiconductor memory device having test mode Static semiconductor memory device having test mode

1998-06-10

2000-07-11

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714718, 365201, G11C 2900, G11C 700

Patent

active

060888202

ABSTRACT:
In an SRAM, a line for applying an internal power supply potential to a memory cell and a line applying an external power supply potential to the portion other than memory cell are separately provided, and an N channel MOS transistor is connected between line for the internal power supply potential and a line for a ground potential. MOS transistor becomes conductive with a predetermined resistance value in a conductive state during test mode. Thus, the potential of line, which has been precharged to internal power supply potential, rapidly decreases to a down-converted potential. Therefore, reduction in time required for a hold test is achieved.

REFERENCES:
patent: 5285418 (1994-02-01), Yamaguchi
patent: 5446694 (1995-08-01), Tanake et al.
patent: 5694364 (1997-12-01), Morishita et al.
patent: 5917765 (1999-06-01), Morishita et al.

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