Method and system for maintaining cache coherence in a multiproc

Details Method and system for maintaining cache coherence in a multiproc Method and system for maintaining cache coherence in a multiproc

1993-12-28

2000-07-11

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711118, 711119, 711130, G06F 1200, G06F 1300

Patent

active

060887680

ABSTRACT:
A method and system for providing cache coherence despite unordered interconnect transport. In a computer system of multiple memory devices or memory units having shared memory and an interconnect characterized by unordered transport, the method comprises sending a request packet over the interconnect from a first memory device to a second memory device requiring that an action be carried out on shared memory held by the second memory device. If the second memory device determines that the shared memory is in a transient state, the second memory device returns the request packet to the first memory device; otherwise, the request is carried out by the second memory device. The first memory device will continue to resend the request packet each time that the request packet is returned.

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