Reduced pin system interface

Details Reduced pin system interface Reduced pin system interface

1997-03-31

2000-07-11

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

395309, 395500, G06F 1200

Patent

active

060887613

ABSTRACT:
The present invention provides an electronic system which includes an integrated circuit chip having a processor, a memory controller and a bus interface. The bus interface is both a memory interface and a system interface and has at least one address pin line, at least one data transfer pin line and at least one control pin line and is coupled to the processor and the memory controller. An S-DRAM is coupled to the bus interface wherein the processor and the S-DRAM share the same address pin line and data transfer pin line reducing the number of pins necessary to interface with the system. A system interface bridge chip interconnects the bus interface to one or more peripheral devices and includes a protocol module for managing interactions on the bus interface between the processor, the S-DRAM and the system interface bridge chip. An electronic system is thus provided which reduces the number of pins that an integrated circuit chip needs for interfacing without reducing performance.

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