Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Patent
1998-03-23
2000-07-11
Chaudhuri, Olik
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With semiconductor element forming part
257698, 257700, 257737, 257738, 438118, H01L 2306
Patent
active
060877170
ABSTRACT:
To completely suppress or minimize the voids formed between the insulating substrate and the IC chip in order to prevent the problems of separation and cracking of the chip caused by the aforementioned voids. The present invention is preferably adopted for the Chip Six Package type package or other package types equipped with solder bumps or other external connecting terminals directly beneath the IC chip. For insulating substrate (3), on its chip-carrying surface, there is pattern element (6) in the region beneath the IC chip and free of conductor pattern elements (4) in addition to conductor pattern element (4) for forming electrical connection between the electrode pads and the external connecting terminals of the chip. Said pattern element (6) divides said region into plural small regions A. IC chip (2) is bonded through die paste on insulating substrate (3) such that an end of conductor pattern element (4), pattern element (6) and divided small regions A are covered. Pattern element (6) acts to reduce the shifting of die paste (9) before curing due to the surface tension. As a result, the formation of voids beneath the chip can be completely prevented or minimized.
REFERENCES:
patent: 5592025 (1997-01-01), Clark et al.
patent: 5616958 (1997-04-01), Laine et al.
Ano Kazuaki
Murata Kensho
Chaudhuri Olik
Donaldson Richard L.
Kempler William B.
Texas Instruments Incorporated
Wille Douglas A.
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