Single polysilicon DRAM cell with current gain

Details Single polysilicon DRAM cell with current gain Single polysilicon DRAM cell with current gain

1998-10-13

2000-07-11

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257336, 257344, 257408, 257322, 257390, H01L 27108, H01L 2976, H01L 2994, H01L 31113

Patent

active

060876905

ABSTRACT:
A single polysilicon DRAM cell is disclosed. The DRAM cell comprises: a deep n-well in a silicon substrate; a p-well within the deep n-well; a gate structure over and straddling the deep n-well and the p-well, the gate structure being a stack of a thin gate oxide layer and a conductive layer; and a n+ well within the p-well and adjacent to a sidewall of the gate structure. The p-well potential can be reset to -V.sub.cc /2 representing "0", and written to V.sub.cc /2 representing "1". The parasitic n-channel MOS with the p-well as the "body" will have a threshold voltage modulated by the p-well potential at V.sub.cc /2 and -V.sub.cc /2 for representing "1" and "0" states, respectively.

REFERENCES:
patent: 4864464 (1989-09-01), Gonzalez
patent: 5378909 (1995-01-01), Chang et al.
patent: 5600598 (1997-02-01), Skjaveland et al.
patent: 5731611 (1998-03-01), Hshieh et al.

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