Insulated gate field effect device

Details Insulated gate field effect device Insulated gate field effect device

1989-02-27

1991-09-10

James, Andrew J.

357 231, 357 233, 357 235, 357 55, H01L 2910, H01L 2978, H01L 2701, H01L 2900

Patent

active

050478125

ABSTRACT:
An insulated gate field effect device is disclosed having a channel region which includes both a horizontal and a vertical portion. The device is fabricated on a semiconductor substrate having a recess formed in its surface. The recess has a bottom forming a second surface with the wall of the recess extending between the first and second surfaces. A source region is formed at the first surface and a drain is formed at the second surface spaced apart from the wall. A channel region is defined along the wall and the second surface between the drain region and the source region. A gate insulator and gate electrode overlie the channel region.

REFERENCES:
patent: 4455740 (1984-11-01), Iwai
patent: 4521795 (1985-06-01), Coe et al.
patent: 4584593 (1986-04-01), Tihanyi
Hockberg et al. "Fabrication of MOS Devices with Close Source Drain Spacing," IBM Tech. Discl. Bulletin, pp. 653-654, Oct. 1967.
Sai-Halasz et al., "Simple Realization of an Edge Doped FET," 11/6/83, p. 3025 of IBM Bulletin.
"Submicron 3D Surface-Orientation-Optimized CMOS Technology", Kinugawa, et al, 1986 VLSI Symposium Digest, pp. 17-18.

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