Wafer-scale integrated circuit interconnect structure architectu

Details Wafer-scale integrated circuit interconnect structure architectu Wafer-scale integrated circuit interconnect structure architectu

1993-12-10

1996-11-19

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

257 50, 257207, 257208, 257209, 257529, 257530, 257503, H01L 2702

Patent

active

055765548

ABSTRACT:
A system for substrate scale integration by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor substrate so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.

REFERENCES:
patent: 3585378 (1969-05-01), Bouricius et al.
patent: 3651473 (1972-03-01), Faber
patent: 3761879 (1973-09-01), Brandsma et al.
patent: 3803562 (1974-04-01), Hunter
patent: 3849872 (1974-11-01), Hubacher
patent: 3983537 (1976-09-01), Parsons et al.
patent: 4007452 (1977-02-01), Hoff, Jr.
patent: 4038648 (1977-07-01), Chesley
patent: 4071887 (1978-01-01), Daly et al.
patent: 4092733 (1978-05-01), Coontz et al.
patent: 4188670 (1980-02-01), Hsia
patent: 4227045 (1980-10-01), Chelcun et al.
patent: 4319356 (1982-03-01), Kocol et al.
patent: 4329685 (1982-05-01), Mahon et al.
patent: 4379327 (1983-04-01), Tietjen et al.
patent: 4407014 (1983-09-01), Holtey et al.
patent: 4458297 (1984-07-01), Stopper et al.
patent: 4467400 (1984-08-01), Stopper
patent: 4494196 (1985-01-01), Greer
patent: 4605928 (1986-08-01), Georgiou
patent: 4615017 (1986-09-01), Finlay et al.
patent: 4627058 (1986-12-01), Moriyama
patent: 4630355 (1986-12-01), Johnson
patent: 4639861 (1987-01-01), Appiano et al.
patent: 4646298 (1987-02-01), Laws et al.
patent: 4653050 (1987-03-01), Vaillancourt
patent: 4663758 (1987-05-01), Lambarelli et al.
patent: 4667328 (1987-05-01), Imran
patent: 4703436 (1987-10-01), Varshney
patent: 4719621 (1988-01-01), May
patent: 4847615 (1989-07-01), McDonald
patent: 4866508 (1989-09-01), Eichelberger et al.
patent: 4872137 (1989-10-01), Jennings, III
patent: 4881232 (1989-11-01), Sako et al.
patent: 4906987 (1990-03-01), Venaleck et al.
patent: 4926382 (1990-05-01), Sakui et al.
patent: 4943914 (1990-07-01), Kubo
patent: 4943966 (1990-07-01), Giunta et al.
patent: 4955020 (1990-09-01), Stone et al.
patent: 4970724 (1990-11-01), Yung
patent: 4974048 (1990-11-01), Chakravorty et al.
patent: 4984192 (1991-01-01), Flynn
patent: 4985895 (1991-01-01), Pelkey
patent: 5020020 (1991-05-01), Pomfret et al.
patent: 5045725 (1991-09-01), Sasaki et al.
patent: 5055897 (1991-10-01), Canepa et al.
patent: 5077596 (1991-12-01), Inoue
patent: 5077737 (1991-12-01), Leger et al.
patent: 5077738 (1991-12-01), Larsen et al.
patent: 5103424 (1992-04-01), Wade
patent: 5111271 (1992-05-01), Hatada et al.
patent: 5111434 (1992-05-01), Cho
patent: 5128737 (1992-07-01), van der Have
patent: 5133064 (1992-07-01), Hotta et al.
patent: 5159273 (1992-10-01), Wright et al.
patent: 5187779 (1993-02-01), Jeddeloh et al.
patent: 5204836 (1993-04-01), Reed
patent: 5214657 (1993-05-01), Farnworth et al.
patent: 5218686 (1993-06-01), Thayer
patent: 5252507 (1993-10-01), Hively et al.
patent: 5261077 (1993-11-01), Duval et al.
Peter van Zant, "Microchip Fabrication," Semiconductor Services, 1986 p. 8.
"A Design and Yield Evaluation Technique for Wafer-Scale Memory", Apr. 1992, Yamashita et al., Fujitsu.
"Task-Flow Architecture for WSI Parallel Processing", Apr. 1992, Robert W. Horst, Tandem Computers Inc.
"A Monolithic Hough Transform Processor Based on Restructurable VLSI", Rhodes et al., Jan. 1988.
"Yield Optimization in Large RAM's with Hierarchical Redundancy", Ganapathy et al., Sep. 1991.
"Wafer-Scale Integration--A Fault-Tolerant Procedure", Aubusson et al., Jun. 1978.
"Designing With the IDT49C460 and IDT39C60 Error Detection and Correction Units", Stodieck, Jan. 1989.
"Reconfiguration of Binary Trees: The Flow-Driven Approach", Antola et al., 1991.
"Large Area Defect-Tolerant Tree Architectures", Shi et al., 1991.

Affiliated with

Also associated with

Rating

Wafer-scale integrated circuit interconnect structure architectu does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer-scale integrated circuit interconnect structure architectu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer-scale integrated circuit interconnect structure architectu will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-542765