Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-10-30
2000-07-11
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438702, 438637, 438638, H01L 214763
Patent
active
060872519
ABSTRACT:
A method for manufacturing a dual damascene structure comprises the following steps. First, a first insulator having a first trench and a second trench therein is formed on a substrate. A first conductive line and a second conductive line are formed in the first trench and the second trench, respectively. A shielding layer is formed on the first conductive line. The upper part of the second conductive line is removed to form a third trench in the first insulator. The shielding layer is removed. A second insulator is formed on the first insulator and thoroughly fills the third trench. Part of the second insulator is removed until the first conductive line is exposed. A dielectric layer is formed on the second insulator and the first conductive line. The dielectric layer is patterned to form a fourth trench and to expose the first conductive line. Finally, a third conductive line is formed in the fourth trench to electrically connect the first conductive line.
REFERENCES:
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patent: 5382545 (1995-01-01), Hong
patent: 5677243 (1997-10-01), Oshaki
patent: 5693568 (1997-12-01), Liu et al.
patent: 5767012 (1998-06-01), Fulford, Jr. et al.
Everhart Caridad
United Microelectronics Corp.
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