Non-volatile memory device

Details Non-volatile memory device Non-volatile memory device

1990-10-22

1993-04-06

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365185, 365210, 36518901, G11C 700

Patent

active

052009238

ABSTRACT:
A non-volatile memory device includes a memory cell array composed of transistor memory cells, a monitor cell array composed of two transistor monitor cells, a first circuit for writing "0" and then "1" in the first monitor cell and a data "1" and then "0" in the second monitor cell, whenever a data is written in one of the memory cells. A second circuit is for applying to the first monitor cell a voltage, V.sub.th1, which is higher than V.sub.th3 applied to the memory cells, and for applying a voltage, V.sub.th2, which is lower than V.sub.th3, to the second monitor cell, in response to a test mode signal, whenever a data is read from the memory cells. A third circuit is for discriminating a margin in the number of data writable operations of the memory cell by detecting monitor cell deterioration. This is accomplished on the basis of the on-off status of the two monitor cells when the second circuit applies V.sub.th1 and V.sub.th2 to the two monitor cells. Therefore, a margin of the memory cells can automatically be indirectly checked by checking a margin of the monitor cells activated under more strict conditions (e.g. the number of operations, threshold voltage, supply voltage, etc.), as compared with the memory cells.

REFERENCES:
patent: 5091884 (1992-02-01), Kagami

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