Automatic reloading of serial read pipeline on last bit transfer

Details Automatic reloading of serial read pipeline on last bit transfer Automatic reloading of serial read pipeline on last bit transfer

1997-08-07

2000-02-22

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711 1, 711105, 711154, 711167, 711202, 711203, 36523001, 36523004, 36523005, 36523009, G06F 1200, G06F 1300

Patent

active

060292350

ABSTRACT:
A video RAM (VRAM) includes a dynamic random access memory (DRAM) having a serial I/O port coupled to a pipelined serial access memory (SAM). The pipelined SAM operates by partitioning a serial read operation into a sensing operation, a counter operation, and an output operation, where all three operations are performed concurrently in a pipelined fashion. The VRAM performs a split read transfer (SRI) operation where data is serially read from one portion of the SAM while new data is transferred from the DRAM to a another portion of the SAM The VRAM recognizes a late SRT operation occurring during the reading of the last bit from one of the SAM portions (known as a last bit transfer), when the address produced by a counter in the counter operation is one past a boundary of one of the SAM portions to invoke circuitry to automatically reload the counter and properly load the SAM pipeline.

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